Architecture
ARM QUIZ - PG-DIoT
Made by @Gayle Fernandes
0
0
7
313
1: 1
25s
16
36
45
21
2: 2
25s
a) 2
c) 4
b) 3
d) 5
3: 3
20s
A) Debugger and Multiplier units are not present
C) Debug and Fast Multiplier units are present
B) Division and Multiplier units are present
D) Division and Multiplier units are not present
4: 4
20s
A) Some form of branching instruction
C) Modifying CPSR
B) Software interrupt
D) None
5: 5
20s
A) The priority level of the interrupt.
C) The Interrupt Service Routine number of the serviced exception
B) Interrupt Service Routine number of the current exception
D) None of the above
6: 6
20s
A) R13, Link register
C) R13, Stack pointer
B) R14, Link register
D) R14, Stack pointer
7: 7
20s
A) Range from (0-255)
C) positive numbers
B) negative numbers
D) None of the above
8: 8
20s
A) RAM
C) Cache Memory
B) Flash memory
D) SRAM
9: 9
20s
A) BASEPRI
C) CONTROL
B) IPSR
D) PC
10: 10
30s
a) 2-5-4-1-3
c) 1-3-2-5-4
b) 2-1-3-4-5
d) 2-4-5-3-1
11: 11
20s
a) Four stages
c) Five stages
b) Three stages
d) Two stages
12: 12
20s
a) PSP as Stack Pointer with unprivileged access
c) PSP as Stack Pointer with privileged access
b) MSP as Stack Pointer with privileged access
d) MSP as Stack Pointer with unprivileged access
13: 13
20s
a) 4
c) 32
b) 16
d) 8
14: 14
20s
A) Both HardFault and NMI are enabled.
C) HardFault is disabled. NMI is enabled.
B) Both HardFault and NMI are disabled.
D) HardFault is enabled. NMI is disabled.
15: 15
20s
A) LDR and STR
C) BLX and BX LR
B) READ and WRITE
D) MSR and MRS
16: 1
25s
16
36
45
21
17: 2
26s
a) 2
c) 4
b) 3
d) 5
18: 3
27s
A) Debugger and Multiplier units are not present
C) Debug and Fast Multiplier units are present
B) Division and Multiplier units are present
D) Division and Multiplier units are not present
19: 4
28s
A) Some form of branching instruction
C) Modifying CPSR
B) Software interrupt
D) None
20: 5
29s
A) The priority level of the interrupt.
C) The Interrupt Service Routine number of the serviced exception
B) Interrupt Service Routine number of the current exception
D) None of the above
21: 6
30s
A) R13, Link register
C) R13, Stack pointer
B) R14, Link register
D) R14, Stack pointer
22: 7
31s
A) Range from (0-255)
C) positive numbers
B) negative numbers
D) None of the above
23: 8
32s
A) RAM
C) Cache Memory
B) Flash memory
D) SRAM
24: 9
33s
A) BASEPRI
C) CONTROL
B) IPSR
D) PC
25: 10
34s
a) 2-5-4-1-3
c) 1-3-2-5-4
b) 2-1-3-4-5
d) 2-4-5-3-1
26: 11
35s
a) Four stages
c) Five stages
b) Three stages
d) Two stages
27: 12
36s
a) PSP as Stack Pointer with unprivileged access
c) PSP as Stack Pointer with privileged access
b) MSP as Stack Pointer with privileged access
d) MSP as Stack Pointer with unprivileged access
28: 13
37s
a) 4
c) 32
b) 16
d) 8
29: 14
38s
A) Both HardFault and NMI are enabled.
C) HardFault is disabled. NMI is enabled.
B) Both HardFault and NMI are disabled.
D) HardFault is enabled. NMI is disabled.
30: 15
39s